As operating speeds and complexity of devices, such as memories, have increased, rates at which data is provided to and received from these devices have also increased. Such increases in data rates, however, are not without their drawbacks. For example, increases in data rates and/or an increasing average number of components in systems have led to increased capacitance on signal busses, for instance, on data busses and data strobe busses. Because the presence of capacitance in excess of particular thresholds may compromise data integrity within a bus or between busses, capacitance can often limit the rate at which data may be provided.
To account for this, several different approaches have been utilized. Wider busses using lower data rates and various bus terminations are examples of ways in which artisans have attempted to address this problem. Yet these and other approaches may not always be feasible solutions due to a variety of reasons, such as available physical space in a device or cost.